Nonvolatile semiconductor memory device capable of storing analog or many-valued data at high speed and with a high degree of accuracy

ABSTRACT

A nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy. 
     The memory device comprises two or more semiconductor devices comprising a first MOS transistor having a first floating gate which is electrically insulated, a first electrode which is capacitively coupled with the first floating gate, a second electrode provided with the first floating gate via a tunnel junction, and a third electrode connected to the second electrode via a switch; the present invention is further provided with a fourth electrode connected commonly with the third electrodes of the semiconductor devices, a fifth electrode connected commonly with the source electrodes of the first MOS transistors, a sixth electrode which is capacitively coupled with the fourth electrode, and a seventh electrode which is connected with the fourth electrode via a switch.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevice, and in particular, relates to a memory device which is capableof storing analog or many-valued data at high speed and with a highdegree of accuracy.

2. Description of the Related Art

In recent years, in concert with the development in computer technology,the progress in the field of data processing technology has been trulyremarkable. However, when attempts were made to realize the flexibletype of data processing conducted by human beings, it was almostimpossible to obtain the results of such calculations in real time usingpresent computers. The reasons advanced for this are that the data whichhuman beings process in the course of their daily lives are analog data,so that there is firstly an enormous amount of such data, and moreover,these data are inexact and vague. It is thus a problem in present dataprocessing systems that the extremely redundant analog data are allconverted into digital values, and rigorous digital operations areconducted one by one.

An example of this is image data. For example, if one screen isincorporated into a 500×500 two dimensional array, then the total numberof pixels is 250,000, and when the strength of the three colors red,green, and blue for each pixel is expressed in terms of eight bits, thenthe amount of data in one stationary image reaches 750,000 bits. Inmoving images, the amount of image data increases with time. Even if apresent day supercomputer is used, it is impossible to manipulate thelarge amount of (1)/(0) data and conduct picture recognition andunderstanding in real time.

On the other hand, attempts have been made to realize data processingapproximating that of human beings by accepting real world data, whichare analog values, in an unchanged form and conducting calculations andprocessing on these analog values, in order to overcome the problemsdescribed above. As a result, a number of memory devices have beeninvented.

As one of these devices, the present inventors have proposed, inJapanese Patent Application No. Hei 7-2944, a memory device which iscapable of writing desired analog values using simple circuitry such asthat shown in FIG. 9 (title of the invention: Nonvolatile semiconductorMemory, date of application: Jan. 11, 1995). First an explanation of thecell of this technology will be made.

Reference 901 indicates an NMOS transistor, while reference 902indicates a floating gate formed from, for example, N⁺ polysilicon; thiscontrols the ON and OFF state of NMOS 901. NMOS drain 903 is connectedto power source line 904, while source 905 is connected to an externalcapacity load 906; the structure is such that the circuit operates as asource follower circuit and reads out a potential V_(FG) of the floatinggate 902 to the exterior as V_(OUT). Reference 907 indicates anelectrode which is capacitively coupled with floating gate 902; in thisexample, it is grounded. The capacitive coupling coefficient thereof isrepresented by C₁. Reference 908 indicates a charge transfer electrode;it is connected with the floating gate via a tunnel junction 909 whichis an oxide film of approximately 10 nm. The capacitance of this tunneljunction 909 is represented by C₂. Charge transfer electrode 908 isconnected to writing high voltage application electrode 911 via acapacitance 910 (the size thereof is represented by C₃). Reference 912indicates an NMOS transistor; the ON and OFF state thereof is controlledby the output line 913 of the inverter. NMOS transistor 914 serves toconnect the input 915 of a control circuit constructed using an inverterto a memory cell. The input 915 of the control circuit is capacitivelycoupled with input of inverter 916, and the input of inverter 916 andoutput 917 are connected via NMOS transistor 918. Output 917 controlsthe ON and OFF state of NMOS transistor 912 via a further stageinverter.

The readout principle is simple; NMOS 914 is placed in an OFF state, andthe memory cell is cut off from the control circuit, and transistor 901is then conducts a source follower operation in the state in whichelectrode 911 is grounded, and the contents of the floating gate areread out as an analog value.

The writing principle will next be explained. During writing, after areference value is first inputted into input 915 of the control circuit,NMOS transistor 918 is first turned ON and is then turned OFF, and thereference value is stored in the input portion of inverter 916, whichhas been placed in a floating state, as a charge, and next, when thereference value is inputted into the control circuit, the controlcircuit outputs the power source voltage to the output line 913. Thisreference value represents the addition of an offset voltage to thevoltage of the data which are to be written, and since the offsetvoltage has a value particular to each circuit, the reference value iseasy to determine.

Next, NMOS 914 is placed in an ON state so that the control circuit maymonitor the output of the source follower. After this, a high voltage ofapproximately 20 V is applied to electrode 911, a strong electric fieldis produced in the tunnel junction 909, and a Fowler-Nordheim current iscaused to flow. The electrons are drawn from the floating gate andwriting commences, and the voltage of the floating gate during thiswriting is inputted into the control circuit via transistor 901 duringthe source follower operation. When the output of the source followerhas become equal to the reference value, the power source voltage isoutputted to the output line of the control circuit and transistor 912,which was in an OFF state, is allowed to conduct. When this is done,electrode 908 is discharged, the strong electric field generated intunnel junction 909 disappears, and writing is completed. At this time,the voltage of the object data is written into the floating gate.

Furthermore, a variety of circuit structures are employed as the controlcircuit, and only one example thereof is discussed here.

FIG. 10 is a circuit diagram showing a plurality of such cells arrangedso as to form an actual memory. The circuit shown in FIG. 9 is employedin an unchanged manner as the control circuit. Of course, other circuitsmaybe employed in some cases.

The reason that a plurality of cells need to be arranged in this way isso that writing may be conducted in such a manner that only the cellinto which writing is to be conducted is selected. References 1001,1002, and 1003 are writing high voltage application electrodes of thecells, respectively, while references 1004, 1005, and 1006 are NMOStransistors used for reading selection. In writing selection, a highvoltage is applied only to the writing voltage application electrode ofthe cell into which writing is to be conducted, while the electrodes ofother cells are set to the ground potential, and only the readingselection transistor of the cell into which writing is conducted isplaced in an ON state, so that the control circuit may monitor only thecontents of the cell into which writing is to be conducted. Byproceeding in this manner, it is possible to cause a tunnel current toflow only in the cell in which writing is to be conducted, and it ispossible to read out the state of only that cell into which writing isconducted to the control circuit.

This memory realizes accurate writing with simple control circuitry; inaddition, there is sufficient selectively in writing and reading,although there is a problem in that the degree of integration does notincrease.

The reason for this is as given below.

C₂ represents the capacitance formed in the tunnel oxide film and sincean extremely thin oxide film is employed, although this capacitancebecomes rather large, it is necessary to set C₁ and C₃ so as to belarger than C₂. The reasons that the design must be accomplished in thismanner are as follows:

(1) In order to apply a large voltage to C₂, it is necessary that C₂ beshown to be small in comparison with C₃ and C₁ ;

(2) C₁ must be made large in comparison with C₂ and C₃ in order tosuppress the rise in voltage in the floating gate resulting fromcapacitive coupling when a high voltage is applied during writing;

(3) It is necessary to set the value of C₃ so as to be considerablylarger than the sum of C₁ and C₂ in order to reduce the voltage dropacross C₂ resulting from the movement of charge during writing. As anexample, appropriate examples are C₁ :C₂ : C₃ =5:1: 25. At this time,the size of the tunnel oxide film is set to 1.5 μm on a side and thethickness thereof is set to 10 nm, and if C₁ is formed between thesubstrate and the first polysilicon layer, then the thickness of theoxide film between these is 50 nm, and the area is 7 μm², while 16 μm²is necessary for C₃. In a structure in which this type of conventionalcell is employed, a large capacitance load such as C₃ is provided foreach cell as shown in FIG. 10 and this is undesirable. It is clear thatas a result of this capacitance alone, the size is not different frompresent DRAM or EEPROM, so that the degree of integration does notincrease.

Furthermore, attempts have been made to omit output selectiontransistors such as 1004, 1005, and 1006 in order to further reduce thenumber of elements. At this time, when power sources 1007, 1008, and1009 are all in operation, output line 1010 is set to the maximum valuemaintained by the floating gate at all times, and selectivity is lostwith respect to reading and with respect to the cell which is monitoredduring writing. Furthermore, if only the power line of the cell which isto be operated is set to the power source voltage, and only one cell isread out, as a result of the voltage rise of voltage line 1010, thepower source side of cells which are not to be read out becomes thesource, and in this state, they enter an ON state, and this isundesirable. The source follower transistors of the cells which are tobe read out also include these and charging is necessary, so that thisleads to a decline in the read out speed.

Accordingly, stratagems are necessary to reduce the number of elements.

FIG. 11 shows a circuit in which the outputs of the cell group shown inFIG. 10 are connected one by one to source follower buffer circuitshaving a CMOS structure. During actual use as a memory, it is necessarythat the memory data be conveyed as far as the operating portions, sothat the source follower of the cells must drive comparatively longwiring. For this reason, it was necessary to connect buffer circuitssuch as those conventionally employed to the memory output portions, asshown by 1101, 1102, and 1103; however, the attachment of buffercircuits to each of the memory outputs further increases the number ofelements required for a memory cell, and thus an increase in the degreeof integration can be anticipated. Furthermore, as a result of variationin the buffer, or the thermal characteristics of the MOS threshold,there were cases in which an accurate readout could not be conducted.

The present invention was created in light of the above circumstances;it has as an object thereof to provide a nonvolatile semiconductormemory which is capable of a high degree of integration and can conductthe writing of analog data at high speed and with a high degree ofaccuracy.

SUMMARY OF THE INVENTION

The present invention is provided with two or more semiconductor devicescomprising a first MOS transistor having a first floating gate which iselectrically insulated, a first electrode which is capacitively coupledwith the first floating gate, a second electrode provided with the firstfloating gate via a tunnel junction, and a third electrode connected tothe second electrode via a switch; the present invention is furtherprovided with a fourth electrode connected commonly with the thirdelectrodes of the semiconductor devices, a fifth electrode connectedcommonly with the source electrodes of the first MOS transistors, asixth electrode which is capacitively coupled with the fourth electrode,and a seventh electrode which is connected with the fourth electrode viaa switch.

In the present invention, capacitances or transistors, one of which wasconventionally required for each memory cell, are externally provided,and the like, and thereby savings is achieved, and by means of this, itis possible to increase the degree of integration compared with theconventional case.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become more apparent and theinvention will be better understood by reference to the followingdescription of an embodiment of the invention taken in conjunction withthe accompanying drawings, wherein:

FIG. 1 is a circuit diagram relating to a first embodiment;

FIG. 2 is a circuit diagram relating to a second embodiment;

FIG. 3 is a circuit diagram relating to a third embodiment;

FIG. 4 is a circuit diagram relating to a fourth embodiment;

FIG. 5 is a circuit diagram relating to a fifth embodiment;

FIG. 6 is a circuit diagram relating to a sixth embodiment;

FIG. 7 is a circuit diagram relating to a seventh embodiment;

FIG. 8 is a circuit diagram relating to an eighth embodiment;

FIG. 9 is a circuit diagram relating to a related technology;

FIG. 10 is a circuit diagram relating to further related technology; and

FIG. 11 is a circuit diagram relating to a related technology.

Corresponding reference characters indicate corresponding partsthroughout the several views. The exemplification set out hereinillustrates one preferred embodiment of the invention, in one form, andsuch exemplification is not to be construed as limiting the scope of theinvention in any manner.

DETAILED DESCRIPTION OF THE INVENTION

Hereinbelow, embodiments of the present invention will be explainedusing the figures.

First Embodiment

FIG. 1 is a circuit diagram showing a first embodiment. Reference 101indicates an NMOS transistor, while reference 102 indicates a floatinggate electrode which is formed from, for example, N⁺ polysilicon; thiscontrols the ON and OFF state of NMOS 101. The drain 103 of the NMOS isconnected to the power source line 104, and source 105 is connected to adrain of NMOS transistor 106, while the source of transistor 106 isconnected to the common readout voltage line 107. Additionally,electrode 108 is the gate electrode of transistor 106. The thresholdvoltage of transistor 106 is represented by V_(FG1), and this is termedthe readout selection transistor. Reference 110 indicates an electrodewhich is capacitively coupled with the floating gate, and thecapacitance coefficient thereof is C₁ ; the potential thereof is set tothe ground potential. Reference 111 indicates an NMOS transistor; thesource electrode thereof is capacitively coupled to a floating gate 102via a tunnel oxide film, and the capacitance coefficient thereof isrepresented by C₂. The drain transistor 111 is connected to a commonwriting voltage generating line 112, and reference 113 indicates thegate electrode of transistor 111. The threshold voltage of thistransistor 111 is represented V_(FG2) and this is termed a writingselection transistor. The structure described above forms one memorycell and a single analog value is stored therein. The various cells arelabeled 114, 115, and 116 from the top of the figure.

In this way, a plurality of identically structured memory cells arecollected, and the structure is such that the source electrode of thereadout selection transistor of each cell is connected to the commonreadout voltage line 107. Furthermore, the drain of the writingselection transistor of each cell is connected to the common writingvoltage generating line 112. Reference 117 is an electrode which iscapacitively coupled with the writing voltage generating line 112, andthe capacitive coupling coefficient thereof is represented by C₃.Furthermore, the common writing voltage generating line 112 is connectedwith the drain of a normally-OFF type NMOS transistor 118, and thesource electrode of transistor 118 is grounded. Additionally, this has agate electrode 120, and the threshold voltage thereof is represented byV_(FG3). Voltage line 107 is connected with the input electrode 122 of acontrol circuit via NMOS transistor 121. The input electrode 122 iscapacitively coupled with input 124 of inverter 123, and furthermore,input 124 is connected with the output 126 of inverter 123 via NMOStransistor 125. The output thereof is connected with gate electrode 120of transistor 118 via another inverter.

Here, N channel transistors are used for all transistors; however, evenif the specified transistors are replaced with P channel MOStransistors, there will be no change whatsoever in the effects of thepresent invention, and furthermore, in FIG. 1, three memory cells arearranged to form one block; however, this was done in order to fit thediagram on the paper, and it is of course the case that the effects ofthe present invention may be obtained when any number of memory cellsgreater than one is employed. Furthermore, in order to simplify theexplanation, the gate electrodes of the writing selection transistors,and the gate electrodes of the readout selection transistors, of thememory cells which were not assigned a number are assigned the numbers127, 128, 129, and 130 and the numbers 131 and 132 are assigned to thetunnel transfer ports thereof. Electrodes 110 and 118 were set to theground potentials; however, this value is not necessarily so restricted,and if a freely selected value is applied, this may be used as astandard, and the other voltages may be adjusted accordingly.

Next, the basic operational principle of the circuit will be explained.Here, the case will be considered in which a voltage V_(TAR) is writteninto only memory cell 114.

V_(REF) is inputted into the control circuit, a single one of which isprovided externally, as a reference voltage. After this, transistor 105is placed in an ON state, and is then placed in an OFF state. When thisis done, the circuit stores the reference voltage, and next, when avalue equivalent to the reference is inputted, the circuit outputs thepower source voltage to gate 120. This value V_(REF) is the value whichis outputted during writing when only V_(TAR) is written into the memorycell; the value thereof represents the addition of an offset voltage toV_(TAR). Since this offset value is determined by the design, it is asimple matter to obtain V_(REF) from V_(TAR). Furthermore, a valuegreater than or equal to threshold voltage V_(FG1) is applied toelectrode 108, while a voltage less than or equal to threshold voltageV_(FG1) is applied to electrodes 129 and 130. When this is done, it ispossible to read out only the contents of the memory cell which is theobject of the writing operation to the common readout voltage 107.

A value greater than or equal to threshold voltage V_(FG2) is inputtedinto electrode 113, while a value less than or equal to thresholdvoltage V_(FG2) is inputted into electrodes 127 and 128. Furthermore,the potential of common writing voltage generating line 112 is set tothe ground potential. By means of preceding in this manner, the tunneltransfer electrodes 131 and 132 of memory cells 115 and 116 store acharge such that they are always at the ground potential, and afterthis, even if the potential of common writing voltage generating line112 changes, the potential of electrodes 131 and 132 does not change.

Next, after transistor 121 has been allowed to conduct, a sufficientlyhigh voltage is applied to electrode 117. This value is approximatelythe value which allows a sufficient current to flow to the tunneljunction of the memory cell during writing. By proceeding in thismanner, a current flows to the tunnel junction of memory cell 114,electrons are drawn from floating gate 102, and the potential of thefloating gate continues to increase. The value of this voltage is readout to the input 122 of the control circuit from the transistor 101which has a source follower structure through the readout selectiontransistor. During the process of writing in this cell, with respect tothe other memory cells, a value less than or equal to V_(FG2) is appliedto electrodes 127 and 128 50 that the writing selection transistorsthereof are in an OFF state, and the tunnel transfer electrodes are inthe previous state, that is say, they store the ground potential. Thatis to say, if attempts are made to conduct writing into memory cell 114,writing is not conducted into cells 115 and 116. It can be seen fromthis that writing is selectively conducted. When writing has beenconducted for a certain amount of time and V_(TAR) is written, thememory cell output V_(REF) at this time.

The values are monitored when necessary by the control circuit, and whenV_(REF) is outputted, the control circuit outputs the power sourcevoltage, and a voltage greater than the threshold voltage is applied togate electrode 120. When this is done, transistor 118 enters an ONstate, and the common writing voltage generating line is discharged, andreaches the ground potential. At this point, the writing is completed.

Furthermore, with respect to the selectivity during readout, this can beeasily accomplished by means of controlling the ON and OFF state of eachreadout selection transistor.

The effects of using this circuit structure are clear. Conventionally,it was necessary that the capacitance C₃ be larger than the othercapacitances C₁ and C₂ ; however, only one such capacitance C₃ wasprovided per block, and a writing selection transistor was used for eachcell, and thereby, it was possible to realize a great increase in thedegree of integration without sacrificing selectivity during writing orreadout. The number of transistors was also much less than theconventional example; three transistors were used per cell.

Furthermore, in the present embodiment, a control circuit was employedin which a switch was provided for short circuiting the output and inputof the inverter; however, there will be absolutely no change in theeffects of the present invention even if other control circuits whichwere conventionally employed are used. This is because the effect of thepresent invention is an increase in integration resulting from makingcommon elements possessed by a number of cells; this effect does notdepend on the structure of the control circuit.

Second Embodiment

FIG. 2 shows a second embodiment. The points of difference between thisembodiment and the first embodiment are that the readout selectiontransistors, one of which was provided for each cell, are eliminated,and furthermore, the potential of the electrode 110, which was fixed atthe ground potential in the first embodiment, is made variable.Furthermore, the identical electrodes of the other memory cells areassigned the numbers 201 and 202, while NMOS transistors controlled bythe floating gate 102 of the other transistors are assigned the numbers203 and 204.

The operation of this circuit will be explained. Now, the case will beconsidered in which a voltage V_(TAR) is written only into memory cell114.

First, V_(REF) is stored in an external control circuit as a referencevoltage. Furthermore, a value greater than or equal to threshold voltageV_(FG1) is applied to electrode 113, while a value less than or equal tothreshold voltage V_(FG1) is applied to electrodes 127 and 128, andwriting only into cell 114 is made possible. Next, 0 V is applied to theelectrode 110 of the cell into which writing is to be conducted, and acertain negative voltage is applied to the electrodes 201 and 202 of theother cells. With respect to the actual value of this negative voltage,any value may be stored in the floating gate; however, this should be avoltage which will definitely place transistors 203 and 204 in an OFFstate. By proceeding in this manner, the values in the floating gates ofthe cells other than memory cell 114 are not read out to the commonreadout power source line, and only the cell which is the object ofwriting can be monitored. If only the cell into which writing is to beconducted can be monitored, writing can be conducted by a mechanismsimilar to that of the first embodiment by reading out this value to thecontrol circuit.

The writing is thus completed; and when only readout is to be conducted,as well, by applying a voltage of 0 V to the cell which is to be readout, while applying a negative voltage to the cells which are not to beread out, it is possible to select only that cell which is to read out.

In this manner, in the second embodiment, by applying a negative voltageto the floating gate via capacitive coupling, it is possible to omit thereadout selection transistors, and thus to realize a further reductionin the number of elements.

Third Embodiment

FIG. 3 shows a third embodiment. The points of difference are that asource follower buffer 301 having a CMOS structure is connected to thecommon readout voltage line of the first embodiment, and the output 302thereof forms the common readout voltage terminal of the data.

The operation of this circuit will be explained. Selective writing isconducted in the same manner as in the first embodiment. The point ofdifference is that the voltage value which passes through the buffer issent to the control circuit during writing, and for this reason, thecorrect value, which has absorbed the dislocation during themanufacturing of the buffer, is written into the memory cell. For thisreason, even if the characteristics of the buffer become aberrant, acorrect value will be written without being affected thereby.

The selective readout is conducted in the same manner as the firstembodiment. The difference is that a buffer is connected to the commonreadout line, and the buffer drives the wiring, so that readout can beconducted at high speed. Furthermore, by means of making the buffercommon to a plurality of memories, an increase in integration ispossible.

The results of using such a circuit structure are clear. Commonly, onebuffer must be assigned to each memory; however, by means of making thebuffer common, a further increase in integration is possible when thecircuit includes such a buffer. Furthermore, the output of the buffer ismonitored by the control circuit during writing, and thereby, theeffects of mistakes made during the manufacturing of the buffer can beeliminated.

Here, a source follower buffer having a CMOS structure was used as thebuffer; however, this is not necessarily so limited, and there is nochange in the effects of the present invention in so far as an amphaving a low impedance output is employed. The reason for this is thatthe effects of the present invention comprise an increase in integrationresulting from making the plurality of buffers common, and this does notdepend on the type of buffer employed.

Fourth Embodiment

FIG. 4 shows a fourth embodiment. The points of difference are that asource follower buffer 401 having a CMOS structure is connected to thecommon readout voltage line 107 of the second embodiment, and the output402 thereof is the common readout voltage terminal of the data.

The operation of this circuit will be explained. The selective writingis conducted in the same manner as in the second embodiment. Thedifference is that the voltage values which have passed through thebuffer are sent to the control circuit during writing, and for thisreason, a correct value which has absorbed the aberrations introducedduring the manufacture of the buffer is written into the memory cell.For this reason, even if the characteristics of the buffer are aberrant,the correct value will be written without being affected thereby.

The selective readout is conducted in the same manner as in the secondembodiment. The difference is that a buffer is connected to the commonreadout line, and since the buffer drives the wiring, readout ispossible at high speed. Furthermore, as a result of making the buffercommon to the plurality of memories, an increase in integration ispossible.

The effects of using this circuit structure are clear. An increase inintegration is possible for two reasons: as a result of the removal ofthe selection transistors, which is the effect of the second embodiment,and as a result of making common the buffer in the case of circuitryincluding a buffer, which is the effect of the third embodiment.

Here, a source follower buffer having a CMOS structure was employed asthe buffer; however, this is not necessarily so limited, and there willbe no change in the effect of the present invention as long as an amphaving a low impedance output is employed. The reason for this is thatthe effects of the present invention comprise an increase in integrationas a result of making the plurality of buffers common, and this is notdependent on the type of buffer employed.

Fifth Embodiment

FIG. 5 shows a fifth embodiment. The drain terminals 501, 502, and 503of the memory cell transistors of memory cells 114, 115, and 116 arecommonly connected to terminal 504, and one terminal of readoutselection transistors 106, 107, and 108 is connected in common toterminal 505. Two P channel transistors 506 and 507 form a currentmirror circuit, and the source thereof is connected to power source 508.An N channel transistor 509 is connected to the drain terminal oftransistor 507. Terminal 505 and the source side terminal of transistor509 are made common, and these are connected to the drain side of nchannel transistor 510, and furthermore, the source thereof is grounded.Terminal 504 is connected to the input 513 of an inversion amplifierformed by a P channel transistor 511 and an N channel transistor 512.Certain voltages are applied to the gate terminals 514 and 515 oftransistors 510 and 512, and the setting is such that this operates as aconstant current source. The output 516 of the inversion amplifier isconnected to the gate of transistor 509, and this point forms the output517 of the memory cell. Output 517 is connected to the input 122 of thecontrol circuit via transistor 121.

Next, the operation of this circuit will be explained. The point ofgreatest difference with the first embodiment is the operation of thecircuit comprising a plurality of transistors which is employed inreadout. First, the operation of this circuit will be explained. Whenonly cell 114 is read out, transistors 107 and 108 are placed in anon-conducting state, and the paths thereof are placed in a closedstate. At this time, a differential amplifier is equivalently formed bytransistors 101, 506, 507, 509, and 510, and the state is such that thegate of transistor 101, that is to say floating gate 102, and terminal517 form the differential input terminal. The output 504 of thedifferential amplifier is connected to the input 513 of the inversionamplifier. That is to say, the circuit which is employed in readout hasterminals 102 and 517 as inputs, and terminal 515 as an output, so thatthis is equivalent to the formation of a type of operational amplifier.

In this case, floating gate 102 serves as the non-inversion inputterminal of the operational amplifier, while terminal 517 forms theinversion input terminal; the output 516 of the operational amplifier isconnected to the inversion input terminal, so that the state isidentical to the formation of a voltage follower having gate 102 as aninput and terminal 517 as an output. Accordingly, the voltage writteninto floating gate 102 appears in an unchanged form in terminal 517.

The writing operation will now be explained. The readout selectivityduring writing is identical to that of the first embodiment; this isconducted by placing transistor 106 in a conducting state, whiletransistors 107 and 108 are placed in a non-conducting state. Theselective high voltage application during writing is also completelyidentical to that of the first embodiment. By applying a high voltage toterminal 117, writing is initiated. The value which is written passesthrough a voltage follower and appears in terminal 517. In exactly thesame manner as in the first embodiment, then this value becomes equal toa reference value V_(REF), the control circuit terminates writing, andthis results the writing of V_(TAR).

The readout operation may also be realized easily by controlling the ONand OFF state of each readout selection transistor 106, 107, and 108.

The effects of using this circuitry will now be explained. The readoutportion comprises a voltage follower having a floating gate as an input,and thus it is possible to obtain all the advantages of a voltagefollower as effects. That is to say, readout is realized in which noeffects are exerted on the outputted value as a result of the thermalcharacteristics of the threshold value of the transistor, and it ispossible to read out correct values irrespective of the operationaltemperature. Furthermore, a low impedance output can be realized, as inthe third and fourth embodiments. Furthermore, as in the third andfourth embodiments, one buffer is provided for a plurality of memorycells, and thereby, it is possible to realize an increase in integrationin the case of a circuit containing a buffer. Furthermore, with respectto offset errors caused by aberrations in the threshold value of thetransistor of the differential input, which is commonly a problem withvoltage followers, by inputting the output of the voltage follower intoa control circuit during writing, correct values incorporating theseerrors can be written into the floating gate of the memory cell, so thatreadout mistakes are not generated as a result of offset errors.

In this way, in the fifth embodiment, a buffer having no thermalcharacteristics changes, termed a voltage follower, is combined withmemory cells, and thereby, it is possible to realize an increase inintegration as a result of making this buffer common, and it is possibleto realize accurate readout.

In the present invention, in the readout circuit, a differentialamplifier having an N channel transistor as input is equivalentlyprovided in the first stage, while an inversion amplifier having aconstant current source load is used in the second stage; however, theinvention is not limited to this type of circuitry. It is clear thatthis is because the effects of the present invention are obtained byproviding a state in which a voltage follower is equivalently formed bythe operational amplifier when the contents of one memory cell are readout, so that this does not depend on the type of operational amplifier.For example, a differential amplification stage having a P channeltransistor as an input in the input portion thereof may be employed, andfurthermore, a differential amplifier stage having a constant resistancein place of the current mirror circuit may be employed. Furthermore, anoperational amplifier employing a folded current mirror circuit may beused.

Sixth Embodiment

FIG. 6 shows a sixth embodiment. The difference between this embodimentand the fifth embodiment is that the readout selection transistors areomitted.

Next, the operation of this circuit will be explained. The operation ofthe circuit is similar to that of the circuit of the fifth embodiment.The difference is that readout selection is conducted by controlling thevoltages of the electrodes 110, 201, and 202 provided in this cell, asin the second embodiment, without the use of readout selectiontransistor switches. The results of using this circuit structure areclearly similar to those of the second embodiment. By omitting thereadout selection transistors which were conventionally necessary, it ispossible to realize a reduction in the number of elements.

Seventh Embodiment

FIG. 7 shows a seventh embodiment. The difference between thisembodiment and the fifth embodiment is that the output terminal 516 ofthe inversion amplifier is connected to the input 701 of a low impedancesource follower buffer having a CMOS structure, and the output 702thereof is connected to terminal 517.

Next, the operation of this circuit will be explained. The operation issimilar to that of the circuit of the fifth embodiment. The differenceis that the output of the operational amplifier is a low impedanceoutput.

The effects of using this type of circuit structure are as follows.Since the output of the operational amplifier has a low impedance, theoutput of the voltage follower also has a low impedance. For thisreason, high speed readout is possible which is resistant to noise.

In the present embodiment, in the readout circuit, a differentialamplifier having an N channel transistor as an input was equivalentlyprovided in the first stage, while a operational amplifier having aninversion amplifier possessing a phase current source load was employedin the second stage; however, the invention is not necessarily limitedto such circuitry. The reason for this is that the effects of thepresent invention are obtained by creating a state in which a voltagefollower is equivalently formed by a operational amplifier having a lowimpedance output when the contents of one memory cell are read out, andit is clear that these effects do not depend on the type of operationalamplifier having a low impedance output which is employed.

Eighth Embodiment

FIG. 8 shows an eighth embodiment. The difference between thisembodiment and the seventh embodiment is that the readout selectiontransistors are omitted.

The operation of this circuit will be explained. The operation issimilar to that of the circuit of the seventh embodiment. The differenceis that readout selection is conducted by controlling the voltages ofelectrodes 110, 201, and 202 provided in the cells as in the secondembodiment, without the use of readout selection transistor switches.

The effects of using this circuit structure are similar to those in thesecond embodiment and are clear. By means of omitting the readoutselection transistors which were conventionally required, it is possibleto realize a reduction in a number of elements.

INDUSTRIAL APPLICABILITY

By means of this circuit, an enormous increase in integration can berealized in comparison with conventional memories.

By means of employing the circuit described in claim 2 as the circuitwhich controls the switches, writing control can be conducted with anextremely small number of elements, and an increase in integration canbe realized.

By means of employing a circuit such as that described in claim 3,signals can be inputted using terminals independent of the circuitrycontrolling the switches, and it is possible to realize a simplificationof the peripheral circuitry.

By means of using circuitry such as that described in claim 4, theeffects of aberrations in the inversion threshold values of theinventors can be ignored, and it is thus possible to ignore variouscauses of inaccuracy arising during circuit manufacture.

By means of using NMOS transistors as switches, circuits can be easilyformed on the same substrate during semiconductor manufacture, and thesame current can be caused to flow in a circuit surface area which issmaller than that in the case in which PMOS transistors are employed, sothat an increase in integration can be realized.

By means of using PMOS transistors as the switches, it is possible toeasily form circuitry on the same substrate during semiconductor circuitmanufacture, and it is possible to form switches which are allowed toconduct when a voltage of 0 V is applied to one gate thereof, andswitches can thus be realized which are capable of control at lowvoltages.

By using NMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and it is possible to allow the same current to flow in asmaller circuit surface area in comparison with the case in which PMOStransistors are employed, so that it is possible to achieve a higherdegree of integration.

By using PMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of 0 V is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By means of using NMOS transistors as switches, it is easily possible toform the circuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of DV is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By means of using NMOS transistors as switches, it is easily possible toform the circuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of DV is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By means of using transmission gates as switches, it is possible torealize a higher degree of accuracy in voltage transmission, and it ispossible to conduct control with a higher degree of accuracy.

In accordance with the present circuit, a much higher degree ofintegration can be achieved than was the case with conventionalmemories.

By means of using circuits such as those described in Claim eleven asthe circuitry which controls the switches, writing control can beconducted with extremely few elements, and a higher degree ofintegration can be realized.

Using elements independent of the circuitry which controls the switches,it is possible to input a signal, and a simplification of the peripheralcircuitry can be realized.

The effects of aberrations in the inversion threshold value of theinverter can be ignored, and it is possible to ignore various sources ofinaccuracies arising during circuit manufacture.

By using NMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and it is possible to allow the same current to flow in asmaller circuit surface area in comparison with the case in which PMOStransistors are employed, so that it is possible to achieve a higherdegree of integration.

By using PMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of 0 V is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By using NMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and it is possible to allow the same current to flow in asmaller circuit surface area in comparison with the case in which PMOStransistors are employed, so that it is possible to achieve a higherdegree of integration.

By using PMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of 0 V is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By using NMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and it is possible to allow the same current to flow in asmaller circuit surface area in comparison with the case in which PMOStransistors are employed, so that it is possible to achieve a higherdegree of integration.

By using PMOS transistors as switches, it is easily possible to form thecircuitry on the same substrate during semiconductor circuitmanufacture, and furthermore, it is possible to form switches which aremade to conduct when a voltage of 0 V is applied to one of the gatesthereof, so that switches can be realized which can be controlled withlow voltages.

By means of using transmission gates as switches, it is possible torealize a higher degree of accuracy in voltage transmission, and it ispossible to conduct control with a higher degree of accuracy.

By means of providing a common low impedance buffer for a plurality ofmemory cells, it is possible to achieve high speed readout, and a higherdegree of integration can be realized than in the case in which a lowimpedance buffer is provided for each memory cell.

By using a source follower having a push-pull structure structured in acomplementary manner using a PMOS transistor and an NMOS transistor asthe low impedance buffer, it is possible to manufacture this in the samemanufacturing process as that of the memory cell.

By means of using a circuit such as that described in claim 25 as thecircuit which controls the switches, it is possible to conduct writingcontrol using extremely few elements, and a high degree of integrationcan be realized.

By means of using a circuit such as that described in claim 26, it ispossible to input signals using a terminal independent of the circuitwhich control the switches, and it is possible to realize asimplification of the peripheral circuitry.

By means of using a circuit such as that described in claim 27, it ispossible to ignore the effects of aberrations in the inversion thresholdvalue of the inverter, and it becomes possible to ignore various sourcesof inaccuracies arising during circuit manufacture.

By means of providing a common low impedance buffer for a plurality ofmemory cells, it is possible to achieve high speed readout, and a higherdegree of integration can be realized than in a case in which a lowimpedance buffer is provided for each memory cell.

By using a source follower having a push-pull structure structured in acomplementary manner using a PMOS transistor and an NMOS transistor asthe low impedance buffer, it is possible to manufacture this in the samemanufacturing process as that of the memory cell.

By means of using a circuit such as that described in claim 30 as thecircuit which controls the switches, it is possible to conduct writingcontrol using extremely few elements, and a high degree of integrationcan be realized.

By means of using a circuit such as that described in claim 31, it ispossible to input signals using a terminal independent of the circuitwhich control the switches, and it is possible to realize asimplification of the peripheral circuitry.

By means of using a circuit such as that described in claim 32, it ispossible to ignore the effects of aberrations in the inversion thresholdvalue of the inverter, and it becomes possible to ignore various sourcesof inaccuracies arising during circuit manufacture.

By providing a common buffer for a plurality of memory cells, it ispossible to realize high speed readout, and furthermore, by causing thisbuffer to conduct a source follower operation of an operationalamplifier, readout and writing which is resistant to noise and drift canbe realized.

By means of using a circuit such as that described in claim 34 as thecircuit which controls the switches, it is possible to conduct writingcontrol using extremely few elements, and a high degree of integrationcan be realized.

By means of using a circuit such as that described in claim 35, it ispossible to input signals using a terminal independent of the circuitwhich controls the switches, and it is possible to realize asimplification of the peripheral circuitry.

By means of using a circuit such as that described in claim 36, it ispossible to ignore the effects of aberrations in the inversion thresholdvalue of the inverter, and it becomes possible to ignore various sourcesof inaccuracies arising during circuit manufacture.

By providing a common buffer for a plurality of memory cells, it ispossible to realize high speed readout, and furthermore, by causing thisbuffer to conduct a source follower operation of an operationalamplifier, readout and writing which is resistant to noise and drift canbe realized.

By means of using a circuit such as that described in claim 38 as thecircuit which controls the switches, it is possible to conduct writingcontrol using extremely few elements, and a high degree of integrationcan be realized.

By means of using a circuit such as that described in claim 39, it ispossible to input signals using a terminal independent of the circuitwhich controls the switches, and it is possible to realize asimplification of the peripheral circuitry.

By means of using a circuit such as that described in claim 40, it ispossible to ignore the effects of aberrations in the inversion thresholdvalue of the inverter, and it becomes possible to ignore various sourcesof in accuracies arising during circuit manufacture.

While this invention has been described as having a preferred design,the present invention can be further modified within the spirit andscope of this disclosure. This application is therefore intended tocover any variations, uses, or adaptations of the invention using itsgeneral principles. Further, this application is intended to cover suchdepartures from the present disclosure as come within known or customarypractice in the art to which this invention pertains and which fallwithin the limits of the appended claims.

What is claimed is:
 1. A nonvolatile semiconductor memory device comprising:two or more semiconductor devices each having a first MOS transistor having a source and having a first floating gate which is electrically insulated;a first electrode capacitively coupled with the first floating gate; a second electrode provided at said first floating gate via a tunnel junction; and a third electrode connected with said second electrode via a switch; wherein a fourth electrode connected commonly with said third electrode of said semiconductor devices; a fifth electrode connected commonly to source of the first MOS transistor; a sixth electrode capacitively coupled with said fourth electrode; and a seventh electrode connected to said fourth electrode via a switch.
 2. A nonvolatile semiconductor memory device in accordance with claim 1 comprising an inverter circuit, wherein the ON and OFF state of said fourth and seventh electrodes is controlled by an output signal, or by a signal resulting from passing an output signal through a pre-specified number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON and OFF state of said other MOS transistor controlled by a second floating gate which is capacitively coupled with an eighth electrode connected with said fifth electrode via a switch.
 3. A nonvolatile semiconductor memory device in accordance with claim 2 including a signal line, wherein the second floating gate is connected to said signal line via a switch.
 4. A nonvolatile semiconductor memory device in accordance with claim 2 including a second inverter circuit with an output terminal, wherein said second floating gate is connected via a switch with said output terminal of said second inverter circuit constructed using at least one other MOS transistor.
 5. A nonvolatile semiconductor memory device in accordance with claim 2 wherein NMOS transistors are used as switches connecting said second and third electrodes.
 6. A nonvolatile semiconductor memory device in accordance with claim 2 wherein PMOS transistors are used as switches connecting said second and third electrodes.
 7. A nonvolatile semiconductor memory device in accordance with claim 2 wherein NMOS transistors are used as switches connecting said fourth and seventh electrodes.
 8. A nonvolatile semiconductor memory device in accordance with claim 2 wherein PMOS transistors are used as switches connecting said fourth and seventh electrodes.
 9. A nonvolatile semiconductor memory device in accordance with claim 2 wherein NMOS transistors are used as switches connecting said fifth and eighth electrodes.
 10. A nonvolatile semiconductor memory device in accordance with claim 2 wherein PMOS transistors are used as switches connecting said fifth and eighth electrodes.
 11. A nonvolatile semiconductor memory device in accordance with claim 2 including transmission gates constructed in a complementary manner using one PMOS transistor and one NMOS transistor are used as said switches connecting said fifth and eighth electrodes.
 12. A nonvolatile semiconductor memory device comprising:two or more semiconductor devices each including:a MOS transistor having a source and having a first floating gate which is electrically insulated; a first electrode capacitively coupled with said first floating gate; a second electrode provided at said first floating gate via a tunnel junction; a third electrode connected to said second electrode via a switch; and a fourth electrode connected to said source of said MOS transistor via a switch; wherein are provided a fifth electrode which is commonly connected to said third electrode of the semiconductor devices; a sixth electrode which is commonly connected to said fifth electrode; a seventh electrode which is capacitively coupled with said fifth electrode; and an eighth electrode which is connected with said fifth electrode via a switch.
 13. A nonvolatile semiconductor memory device in accordance with claim 12 including an inverter circuit and wherein the ON and OFF state of said fifth electrode and said eighth electrode are controlled by an output signal, or by a signal resulting from passing said output signal through a prescribed number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON and OFF state of which is controlled by a second floating gate capacitively coupled with a ninth electrode which is connected with said sixth electrode via a switch.
 14. A nonvolatile semiconductor memory device in accordance with claim 13 includes a signal line and wherein said second floating gate is connected to said signal line via a switch.
 15. A nonvolatile semiconductor memory device in accordance with claim 13 wherein said second floating gate is connected via a switch to an output terminal of said inverter circuit constructed using at least one other MOS transistor.
 16. A nonvolatile semiconductor memory device in accordance with claim 13 wherein an NMOS transistor is used as the switch connecting said second and third electrodes.
 17. A nonvolatile semiconductor memory device in accordance with claim 13 wherein a PMOS transistor is used as the switch connecting said second and third electrodes.
 18. A nonvolatile semiconductor memory device in accordance with claim 13 wherein an NMOS transistor is used as the switch connecting said fifth and eighth electrodes.
 19. A nonvolatile semiconductor memory device in accordance with claim 13 wherein a PMOS transistor is used as the switch connecting said fifth and eighth electrodes.
 20. A nonvolatile semiconductor memory device in accordance with claim 13 wherein an NMOS transistor is used as the switch connecting said sixth and seventh electrodes.
 21. A nonvolatile semiconductor memory device in accordance with claim 13 wherein a PMOS transistor is used as the switch connecting said sixth and seventh electrodes.
 22. A nonvolatile semiconductor memory device in accordance with claim 13 wherein a transmission gate is constructed in a complementary manner using a PMOS transistor and an NMOS transistor and used as a switch connecting said sixth and ninth electrodes.
 23. A nonvolatile semiconductor memory device comprising:two or more semiconductor devices including:a MOS transistor having a source and having a first floating gate which is electrically insulated; a first electrode which is capacitively coupled with said first floating gate; a second electrode provided at said first floating gate via a tunnel junction; and a third electrode which is connected with said second electrode via a switch; wherein are provided: a fourth electrode which is commonly connected with said third electrode of the semiconductor devices; a fifth electrode which is commonly connected with the source of said MOS transistor; a sixth electrode which is capacitively coupled with said fourth electrode; a seventh electrode which is connected with said fourth electrode via a switch; and an eighth electrode which is connected with said fifth electrode via a buffer circuit having a low impedance output.
 24. A nonvolatile semiconductor memory device in accordance with claim 23, including a source follower having a push-pull structure constructed in a complementary manner using a PMOS transistor and an NMOS transistor employed as a buffer having a low impedance output which connects said fifth and eighth electrodes.
 25. A nonvolatile semiconductor memory device in accordance with claim 24, including an inverter circuit, wherein the ON/OFF state of the fourth and seventh electrodes is controlled by an output signal, or by a signal resulting from passing said output signal through a predetermined number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON/OFF state of which is controlled by a second floating gate which is capacitively coupled with a ninth electrode which is connected to said eighth electrode via a switch.
 26. A nonvolatile semiconductor memory device in accordance with claim 24 including a signal line, wherein said second floating gate is connected to said signal line via a switch.
 27. A nonvolatile semiconductor memory device in accordance with claim 24, wherein said second floating gate is connected via a switch to an output terminal of said inverter circuit constructed using at least one other MOS transistor.
 28. A nonvolatile semiconductor memory device comprising:two or more semiconductor devices including:an MOS transistor having a source and having a first floating gate which is electrically insulated; a first electrode which is capacitively coupled with said first floating gate; a second electrode provided at said first floating gate via a tunnel junction; a third electrode connected to said second electrode via a switch; and a fourth electrode connected with the source of said MOS transistor via a switch; wherein are provided: a fifth electrode commonly connected with said third electrode of the semiconductor devices; a sixth electrode commonly connected with said fourth electrode; a seventh electrode capacitively coupled with said fourth electrode; an eighth electrode connected with said fourth electrode via a switch; and a ninth electrode connected with said sixth electrode via a buffer circuit having a low impedance output.
 29. A nonvolatile semiconductor memory device in accordance with claim 28, wherein a source follower having a push-pull structure structured in a complementary manner using a PMOS transistor and an NMOS transistor is used as said buffer circuit having a low impedance output which connects said sixth and ninth electrodes.
 30. A nonvolatile semiconductor memory device in accordance with claim 29, including an inverter circuit, wherein the ON/OFF states of said fourth and eighth electrodes are controlled by an output signal, or by a signal resulting from passing said output signal through a prescribed number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON/OFF state of which is controlled by a second floating gate which is capacitively coupled with a tenth electrode connected to said ninth electrode via a switch.
 31. A nonvolatile semiconductor memory device in accordance with claim 30 wherein said second floating gate is connected to a signal line via a switch.
 32. A nonvolatile semiconductor memory device in accordance with claim 29 wherein said second floating gate is connected via a switch to an output terminal of said inverter circuit constructed using at least one other MOS transistor.
 33. A nonvolatile semiconductor memory device comprising:at least two semiconductor devices each including:a MOS transistor having a source, a drain and having a first floating gate which is electrically insulated; a first electrode which is capacitively coupled with said first floating gate; a second electrode which is provided at said first floating gate via a tunnel junction; and a third electrode which is coupled with said second electrode via a switch; wherein are provided: a fourth electrode which is commonly connected to said third electrode of the semiconductor devices; a fifth electrode which is commonly connected to the source of said MOS transistor; a sixth electrode which is commonly connected to the drain of said MOS transistor; a first operational amplifier; and wherein the source of said MOS transistor receives a non-inversion input of said first operational amplifier is connected to said fifth electrode, while the drain thereof is connected to said sixth electrode, an inversion input of said first operational amplifier is connected to an output of said first operational amplifier, and said fifth electrode is capacitively coupled with said fourth electrode, and said sixth electrode, said fifth electrode connected via a switch with said fourth electrode.
 34. A nonvolatile semiconductor memory device in accordance with claim 33, including an inverter circuit and wherein the ON/OFF states of said fourth and sixth electrodes are controlled by an output signal, or by a signal resulting from passing the output signal through a predetermined number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON/OFF state of which is controlled by a second floating gate which is capacitively coupled with a seventh electrode, which is connected by a switch with the output of said first operational amplifier.
 35. A nonvolatile semiconductor memory device in accordance with claim 34, wherein said second floating gate is connected to a signal line via a switch.
 36. A nonvolatile semiconductor memory device in accordance with claim 34, wherein said second floating gate is connected via a switch to an output terminal of said inverter circuit constructed using at least one other MOS transistor.
 37. A nonvolatile semiconductor memory device comprising:two or more semiconductor devices each including:a MOS transistor having a source, a drain and having a first floating gate which is electrically insulated; a first electrode capacitively coupled with said first floating gate; a second electrode provided at said first floating gate via a tunnel junction; a third electrode coupled with said second electrode via a switch; and a fourth electrode connected to the source of said MOS transistor via a switch; wherein a fifth electrode commonly connected to said third electrode of the semiconductor devices; a sixth electrode commonly connected to said fourth electrode; a first operational amplifier; and a seventh electrode commonly connected to the drain of said MOS transistor, and wherein the source of said MOS transistor receives a non-inversion input of said first operational amplifier and is connected to said sixth electrode, while the drain thereof is connected to said seventh electrode, and an inversion input of said first operational amplifier is connected to an output of said first operational amplifier, and said seventh electrode is capacitively coupled with said fifth electrode, and said sixth electrode, which is also connected via a switch with said fifth electrode.
 38. A nonvolatile semiconductor memory device in accordance with claim 37, including an inverter circuit, wherein the ON/OFF state of said fifth and sixth electrodes are controlled by an output signal, or by a signal resulting from passing an output signal through a pre-specified number of inverter stages, of said inverter circuit constructed using at least one other MOS transistor, the ON/OFF state of which is controlled by a second floating gate capacitively coupled with an eighth electrode, which is connected to the output of said first operational amplifier via a switch.
 39. A nonvolatile semiconductor memory device in accordance with claim 38, including a signal line, wherein said second floating gate is connected to said signal line via a switch.
 40. A nonvolatile semiconductor memory device in accordance with claim 38, wherein said second floating gate is connected via a switch with an output terminal of said inverter circuit constructed using at least one other MOS transistor. 